Analog Layout Engineer

Responsibilities: Collaborate with remote circuit designers to define and optimize chip floorplans, focusing on Develop schedules and execution plans to ensure timely project completion within defined timelines. Interpret and apply foundry design documents to resolve layout challenges, including latch-up prevention and DRC compliance. Perform custom layout using Cadence Virtuoso , ensuring LVS/DRC-clean designs. Utilize CAD tools such as Virtuoso , Calibre LVS/DRC , SkillCad , etc., effectively throughout the layout process. Contribute to chip-level layout tasks, including bump, pad, and ESD strategies . Communicate effectively with remote design teams through verbal discussions and well-documented written communication when real-time interaction is not feasible. Preferred Skills: Experience working with advanced process nodes (28nm, 22nm, 14nm, 8nm, 5nm, and below). Familiarity with high-frequency IC layouts up to 40GHz . Hands-on experience with critical analog/RF blocks such as VCO, LNA, PA , etc. Proficient in Linux environments and CAD tools including Cadence Virtuoso , Calibre LVS/DRC , and SkillCad . Excellent verbal and written communication skills, including the ability to document layout methodologies and communicate design intent clearly. Ability to work independently and take ownership of layout tasks. Leadership experience is a plus—especially in leading small teams and managing analog IC tapeouts .

Information :

• Company : BITSILICA
• Position : Analog Layout Engineer
• Location : Bangalore, Karnātaka
• Country : IN