Senior Design Verification Engineer

JD for DV lead:

• 7+ years of hands-on DV experience in SystemVerilog/UVM.
• Must be able to own and drive the verification of a block / subsystem or a SOC.
• Should have a track record of leading a team of engineers.
• Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM.
• Experience in Tesplan and Testbench development,
• Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time.
• Should be good with debugging and exposed to all aspects of verification flow including Gatesims
• Must have extensive experience in verification of one or more of the following:
• PCI Express or UCIe, CXL or NVMe
• AXI, ACE or CHI
• Ethernet, RoCE or RDMA
• DDR or LPDDR or HBM
• ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages
• Power Aware Simulations using UPF
• Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper.
• Experience in using one or more of revision control systems such as: Git, Perforce, Clearcase.
• Experience in SVA and formal verification is desirable (not a must)
• Script development using Python, Perl or TCL is desirable (not a must)

Information :

• Company : Taggd
• Position : Senior Design Verification Engineer
• Location : Bangalore, Karnātaka
• Country : IN