| Position | IP Verification Engineer |
| Posted | 2025 October 23 |
| Expired | 2025 November 22 |
| Company | ACL Digital |
| Location | Hyderabad | IN |
| Job Type | Full Time |
Latest job information from ACL Digital for the position of IP Verification Engineer. If the IP Verification Engineer vacancy in Hyderabad matches your qualifications, please submit your latest application or CV directly through the updated Jobkos job portal.
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IP Verification Engineer Experience : 5-7 years Location : Hyderabad Job Description:System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol. Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers. Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging. Basic Job Deliverable:Setup verification environment and bring up simulations with various simulations such as VCS / Questa / Xcellium / Riviera SV/UVM Functional verification Expertise in Vivado for simulation debugs Interested,please drop your CV to janagaradha.n@acldigital.comAfter reading and understanding the criteria and minimum qualification requirements explained in the job information IP Verification Engineer at the office Hyderabad above, immediately complete the job application files such as a job application letter, CV, photocopy of diploma, transcript, and other supplements as explained above. Submit via the Next Page link below.
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